1. Field of the Invention
The present invention relates to an output circuit of a semiconductor memory device and more particularly, to an output circuit of a semiconductor memory device that outputs a pair of complementary data signals read out from a memory cell array of the semiconductor memory device.
2. Description of the Prior Art
In recent years, various Dynamic Random-Access Memories (DRAMs ) having the "Extended Data Output (EDO)" function have been developed and practically used in the various application fields. This is because the DRAMs with the EDO function operate faster than the well-known "Fast-Page" mode DRAMs.
The "EDO" function is a function that the output behavior of the data signal that have been read out from the memory cell is continued during a specific period in a read cycle even after an external clock signal for controlling the output behavior is reset to specify a new column address. This is unlike the well-known "Fast-Page" mode DRAMs in which the output behavior of the data signal that have been read out from the memory cell is stopped in a read cycle synchronized with the reset of the external clock signal. As the external clock signal, a Column Address Strobe (CAS) signal is typically used.
In the DRAMs with the EDO function, accordingly, it is necessary for the output circuits to hold the data signal that has been read out from the memory cell during a specific period synchronized with an input pulse signal for the output circuits. As the input pulse signal for the output circuits, an Output Enable (OE) signal is typically used.
A conventional output circuit of a DRAM with the EDO function is shown in FIG. 1, which is comprised of a switching section, a data latch section, a driver section, and an output section.
The switching section has first and second transfer gates 701 and 702. The first transfer gate 701 is formed by a p-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) 701a and an n-channel MOSFET 701b. Sources of the MOSFETs 701a and 701b are coupled together to be connected to a first input terminal T.sub.71. Drains of the MOSFETs 701a and 701b are coupled together to be connected to a first node 71. Similarly, the second transfer gate 702 is formed by a p-channel MOSFET 702a and an n-channel MOSFET 702b. Sources of the MOSFETs 702a and 702b are coupled together to be connected to a second input terminal T.sub.72. Drains of the MOSFETs 702a and 702b are coupled together to be connected to a second node 72.
The first input terminal T.sub.71 is connected to a first read bus (not shown) of the DRAM and is applied with a first read bus data signal RBST. The second input terminal T.sub.72 is connected to a second read bus (not shown) of the DRAM and is applied with a second read bus data signal RBSN complementary to the first read bus data signal RBST.
The switching section further includes three cascade-connected inverters 712a, 712b, and 713 for controlling the transfer gates 701 and 702, in which the inverters 712a and 712b serve as a buffer circuit. An input of the inserter 712a is connected to a third input terminal T.sub.73. An output of the inverter 712a is connected to an input of the inverter 712b. An output of the inverter 712b is connected to an input of the inverter 713 and a gate of the MOSFET 701a of the first transfer gate 701 and a gate of the MOSFET 702a of the second transfer gate 702. An output of the inverter 713 is connected to a gate of the MOSFET 701b of the first transfer gate 701 and a gate of the MOSFET 702b of the second transfer gate 702.
The third input terminal T.sub.73 is connected to a clock generator (not shown) of the DRAM and in applied with a transfer-gate control signal .phi..
The inverter 712b outputs a transfer-gate control signal TG to the inverter 713 and the gates of the MOSFETs 701a and 702a according to the applied transfer control signal .phi.. The inverter 713 outputs an inverted transfer-gate control signal TG to the gates of the MOSFETs 701b and 702b according to the applied transfer-gate control signal TG.
The first and second transfer gates 701 and 702 are controlled by the transfer-gate control signal TG and the inverted transfer-gate control signal TG, thereby transferring the first and second read bus data signals RBST and RBSN to the first and second nodes 71 and 72, respectively.
The data latch section has first and second flip-flops 705 and 706. The first flip-flop 705 is formed by two inverters 705a and 705b connected in cascade to make a loop. An input and an output of the inverter 705a are connected to the first node 71 and an input of the inverter 705b, respectively. An output of the inverter 705b is connected to the first node 71. Similarly, the second flip-flop 706 is formed by two inverters 706a and 706b connected in cascade to make a loop. An input and an output of the inverter 706a are connected to the second node 72 and an input of the inverter 706b, respectively. An output of the inverter 706b is connected to the second node 72.
The first flip-flop 705 temporarily holds or latches the applied read bus data signal RBST at the first node 71. The first read bus data signal RBST thus latched in the first flip-flop 705 is termed a first read bus data signal RBST'.
Similarly, the second flip-flop 706 temporarily holds or latches the second read bus data signal RBSN at the second node 72. The second read bus data signal RBSN thus latched in the second flip-flop 706 is termed a second read bus data signal RBSN'.
The driver section has first and second transistor drivers 708 and 709 and an inverter 715. The first transistor drivers 708 is formed by a NOR gate 708a and an inverter 708b. First and second inputs of the NOR gate 708a are connected to the first node 71 and an output of the inverter 715, respectively. An output of the NOR gate 708a is connected to an input of the inverter 708b. An output of the inverter 708b is connected to a gate of a p-channel output MOSFET 710. The second driver circuit 709 is formed by a NOR gate 709a. First and second inputs of the NOR gate 709a are connected to the second node 72 and the output of the inverter 715, respectively. An output of the NOR gate 709a is connected to a gate of an n-channel output MOSFET 711.
An input of the inverter 715 is connected to a fourth input terminal T.sub.74 to which an output-enable signal OE is applied. The inverter 715 serves as a buffer circuit for the signal OE. The inverter 715 outputs an inverted Output Enable signal OE according to the applied signal OE to the second inputs of the NOR gates 708a and 709a.
In response to the first read bus data signal RBST' and the inverted output-enable signal OE, the first driver 708 outputs a first driving signal OUTT to the gate of the p-channel MOSFET 710. In response to the second read bus data signal RBSN' and the inverted output-enable signal OE, the second driver 709 outputs a second driving signal OUTN to the gate of the n-channel MOSFET 711.
The output section has the p- and n-channel MOSFETs 710 and 711 serving as output transistors. A source of the MOSFET 710 is connected to a power supply line applied with a power supply voltage V.sub.DD. A drain of the MOSFET 710 is connected to a drain of the MOSFET 711. A source of the MOSFET 711 is connected to the ground. The gate of the MOSFET 710 is connected to the output of the inverter 708b of the first driver 708. The gate of the MOSFET 711 is connected to the output of the NOR gate 709a of the second driver 709. The coupled drains of the MOSFETs 710 and 711 are connected to an output terminal T.sub.75 through which an output data signal DOUT is derived.
When the p-channel output MOSFET 710 is in the ON state and the n-channel output MOSFET 711 is in the OFF state, the output data signal DOUT is equal to the power supply voltage V.sub.DD. On the other hand, when the n-channel output MOSFET 711 is in the ON state and the p-channel output MOSFET 710 is in the OFF state, the output data signal DOUT is equal to the ground potential (GND), i.e., zero.
Next, the operation of the conventional output circuit of FIG. 1 is explained below with reference to FIGS. 2A to 2L.
FIGS. 2A to 2L are timing diagrams showing the waveforms of the signals used in the conventional output circuit shown in FIG. 1.
Here, it is supposed that a Row Address Strobe (RAS) signal has been already activated and that a desired row address has been already fetched and that the data signals corresponding to the specified row address have been amplified by a sense amplifier (not shown). A data signal corresponding to a column specified by a CAS signal is selected from the data signals corresponding to the specified row address and then, it is transmitted to the first and second read bus lines.
FIG. 2A shows the signal CAS serving as an external clock signal. FIG. 2B shows a column address signal ADD. FIG. 2C shows the transfer control signal .phi. applied to the third input terminal T.sub.73, which is synchronized with the external clock signal CAS shown in FIG. 2A. FIGS. 2D and 2E show the first and second read bus data signals RBST and RBSN transmitted through the first and second input terminals T.sub.71 and T.sub.72, respectively, in which these two signals RBST and RBSN are complementary. FIG. 2F shows the transfer-gate control signal TG, which is generated from the transfer control signal .phi.. FIGS. 2G and 2H show the first and second read bus data signals RBST' and RBSN' latched in the first and second flip-flops 705 and 706, respectively, in which these two signals RBST' and RBSN' are complementary. FIG. 2I shows the output-enable signal OE. FIGS. 2J and 2K show the first and second driving signals OUTT and OUTN, respectively. FIG. 2L shows the output data signal DOUT.
If the column address signal ADD is activated (i.e., turned from the low logic state L to the high logic state H, or turned from the high logic state H to the low logic state L) at the time T1, as shown in FIG. 2B, the second read bus data signal RBSN is turned from the low logic state L to the high logic state H at the time T3, as shown in FIG. 2E. At this time, the first read bus data signal RBST is kept at the high logic state H, as shown in FIG. 2D.
Then, at the time T5, the first read bus data signal RBST is turned from the logic state H to the logic state L, as shown in FIG. 2D.
When the external clock signal CAS is turned from the logic state H to the logic state L (i.e., activated) at the time T6 according to the change of the column address signal ADD, the transfer control signal .phi. is turned to the logic state L at the time T7. Accordingly, the transfer-gate control signal TG is turned to the logic state L at the time T9 and the first and second transfer gates 701 and 702 are opened, thereby transferring the first and second read bus data signals RBST and RBSN to the first and second nodes 71 and 72, respectively, as shown in FIGS. 2D and 2E.
Thus, the first read bus data signal RBST' latched at the first node 71 is turned from the logic state H to the logic state L at the time T10 and at the same time, the second read bus data signal RBSN' latched at the second node 72 is turned from the logic state L to the logic state H, as shown in FIGS. 2G ad 2H.
Due to the latched read bus data signals RBST' and RBSN', the second driving signal OUTN is turned from the logic state H to the logic state L at the time T11, and the first driving signal OUTT is turned from the logic state H to the logic state L at the time T12, as shown in FIGS. 2J and 2K. Thus, the n-channel MOSFET 711 is turned to the OFF state and the p-channel MOSFET 710 is turned to the ON state. The first and second driving signals OUTT and OUTN are not affected by the output-enable signal OE, because the output-enable signal OE is always fixed at the logic state H during the read out cycles, as shown in FIG. 21.
As a result, the output signal DOUT is turned from the logic state L to the logic state H at the time T14, as shown in FIG. 2L.
Following this step, the external clock signal CAS is turned to the logic state H (i.e., the signal CAS is reset) at the time T16. In response to this change of the signal. CAS, the transfer control signal .phi. is turned to the logic state H at the time T17. Due to the change of the signal .phi., the transfer-gate control signal TG is turned to the logic state H at the time T19, thereby separating the first and second read buses from the first and second flip-flops 705 and 706. At this stage, the first and second read bus data signals RBST' and RBSN' are latched by the first and second flip-flops 705 ad 706 and therefore, the output data signal DOUT is kept in the logic state H. This means that the EDO function is realized.
Subsequently, to start a next read cycle, the column address signal ADD is activated (i.e., turned from the logic state L to the logic state H, or turned from the logic state H to the logic state L) at the time T20. Then, the first read bus data signal RBST is turned from the logic state L to the logic state H at the time T22. At this time, the second read bus data signal RBSN is kept at the logic state H.
Then, at the time T24, the first read bus data signal RBSN is turned from the logic state H to the logic state L.
When the external clock signal CAS is turned from the logic state H to the logic state L (i.e., activated) at the time T25 according to the column address signal ADD, the transfer control signal .phi. is turned to the logic state L at the time T26. Thus, the transfer-gate control signal TG is turned to the logic state L at the time T28, thereby transferring the first and second read bus data signals RBST and RBSN to the first and second nodes 71 and 72, respectively.
Thus, the second read bus data signal RBSN' latched at the second node 72 is turned from the logic state H to the logic state L at the time T29 and at the same time, the first read bus data signal RBST' latched at the first node 71 is turned from the logic state L to the logic state H, as shown in FIGS. 2G and 2H.
Due to the latched read bus data signals RBST' and RBSN', the second driving signal OUTN is turned from the logic state L to the logic state H at the time T30, and the first driving signal OUTT is turned from the logic state L to the logic state H at the time T31. Thus, the n-channel output MOSFET 711 is turned to the ON state and the p-channel output MOSFET 710 is turned to the OFF state.
As clearly seen from FIGS. 2J, 2K and 2L, both of the first and second driving signals OUTN and OUTT are at the logic state L during the time period from T30 to T31. Therefore, both of the n- and p-channel MOSFETs 711 and 710 are kept in the ON state (i.e., in the ON-ON state) during the time period T from T30 to T31, as shown in FIG. 2L. In other words, the power supply line and the ground line are in short-circuit. Accordingly, a large current flows from the power supply line to the ground through the MOSFETs 710 and 711 and as a result, the level of the output signal DOUT lowers gradually, as shown in FIG. 2L.
Subsequently, to read out a next data, the external clock signal CAS is turned to the logic state H for resetting at the time T35. In response to this change of the signal CAS, the transfer control signal .phi. is turned to the logic state H at the time T36. Due to the change of the transfer control signal .phi., the transfer-gate control signal TG is turned to the logic state H at the time T38, thereby separating the first and second read buses from the first and second flip-flops 705 and 706.
At this stage, the first and second read bus data signals RBST' and RBSN' are latched by the first and second flip-flops 705 ad 706 and therefore, the output data signal DOUT is kept in the logic state L for the purpose of the EDO function.
After the time T38, the same procedure as above is repeated.
As explained above, with the conventional output circuit in FIG. 1, both of the n- and p-channel MOSFETs 711 and 710 are kept in the ON state (i.e., in the ON-ON state) during the time period T from T30 to T31. Therefore, a problem that a large current flows from the power supply line to the ground line through the p- and n-channel output MOSFETs 710 and 711 during the period T will occur.
Also, the current flowing from the power supply line to the ground line changes the power supply level and the ground level. Therefore, the operation of the output circuit itself is badly affected.
Additionally, a different operation may be performed in the conventional output circuit in FIG. 1, as shown in FIGS. 3A to 3L, which illustrate the waveforms of the signals used in the conventional output circuit of in FIG. 1.
In this operation, to prevent the ON-ON state of the p- and n-channel MOSFETs 710 and 711 from occurring by the first and second driving signals OUTT and OUTN, the output-enable signal OE is clocked to be synchronized with the external clock signal CAS, as show in FIG. 3I.
The timing diagrams of the signals CAS, ADD, .phi., RBST, RBSN, TG, RBST', and RBSN' are same as those in FIGS. 2A to 2H, respectively. Therefore, the explanation about those signals are omitted here for simplification.
When the external clock signal CAS is activated at the time T6, as shown in FIG. 2A, the output-enable signal OE is turned from the logic state H to the logic state L at the time T8, as shown in FIG. 3A. The timing of the change of the signal OE is prior to the time T10 on which the level of the latched data signals RBST' and RBSN' are changed.
Due to the change of the signal OE, the inverted output-enable signal OE is turned from the logic state L to the logic state H, thereby turning the second driving signal OUTN to the logic state L at the time T10. Thus, the n-channel MOSFET 711 is turned OFF, resulting in the OFF-OFF state of the p- and n-channel MOSFETs 710 and 711.
In the same way as that of the above-described operation using FIGS. 2A to 2L, the latched data signals RBST' and RBSN' are changed at the time T10, as shown in FIGS. 2G and 2H. However, the change of the signals RBST' and RBSN' is not transferred to the output MOSFETs 710 and 711, because the output-enable signal OE is in the logic state L. Thus, the output signal DOUT is kept in the logic state L at this stage.
Subsequently, if the output-enable signal OE is turned to the logic state H at the time T12, the first driving signal OUTT is turned from the logic state H to the logic state L at the time T15, as shown in FIGS. 3A and 3B. Thus, the p-channel MOSFET M710 is turned ON, as shown in FIG. 3D, which results in the ON state of the p-channel MOSFET 710 while the n-channel MOSFET 711 is kept in the OFF state. Consequently, the output signal DOUT is turned to the logic state H at the time T17.
If the external clock signal CAS is turned to the logic state L again at the time T25, the output-enable signal OE is turned from the logic state H to the logic state L at the time T27. The timing of the change of the signal OE is prior to the time T29 on which the level of the latched data signals RBST' and RBSN' are changed. This is due to the fact that the ON-ON state of the output MOSFETs 710 and 711 will occur if the signal OE is changed after the time T29.
In the same way as that of the above-described operation shown in FIGS. 2A to 2L, the latched data signals RBST' and RBSN' are changed at the time T29, as shown in FIGS. 2G and 2H. However, the change of the signals RBST' and RBSN' is not transferred to the output MOSFETs 710 and 711, because the output-enable signal OE is in the logic state L. Thus, the output signal DOUT is kept in the logic state H at this stage.
Due to the change of the output-enable signal OE at the time T27, the inverted output-enable signal OE is turned from the logic state L to the logic state H, thereby turning the first driving signal OUTT to the logic state H at the time T30. Thus, the p-channel MOSFET 710 is turned OFF, resulting in the OFF-OFF state of the p- and n-channel MOSFETs 710 and 711 at the time T30.
Subsequently, the output-enable signal OE is turned to the logic state H again at the time T31, which turns the second driving signal OUTN to the logic state H at the time T33 while keeping the first driving signal OUTT in the logic state H. Thus, the n-channel MOSFET M711 is turned ON at the time T33 while the p-channel MOSFET 710 is kept OFF. Consequently, the output data signal DOUT is turned to the logic state L at the time T35.
As explained above, in the operation shown in FIGS. 3A to 3D, the change of the first and second latched signals RBST' and RBSN' are not transferred to the p- and n-channel output MOSFETs 710 and 711 during the times T27 to T31 in which the output-enable signal OE is in the logic state L. In other words, the first driving signal OUTT is turned to the logic state H (i.e., the p-channel MOSFET is turned OFF) at the time T30 due to the signal OE before the second driving signal OUTN is turned to the logic state H (i.e., the n-channel MOSFET is turned ON) at the time T33.
Accordingly, the ON-ON state of the p- and n-channel output MOSFETs 710 and 711 are prevented from oocurring.
However, the operation shown in FIGS. 3A to 3D has the following problem.
Specifically, it is popular that the output-enable signal OE is generated in a separated circuit block from the conventional output circuit shown in FIG. 1 and then, the signal OE is inputted into this output circuit. Therefore, the timing of change of the output-enable signal OE tends to be shifted or deviated in time with respect to the timing of change of the latched signals RBST' and RBSN' due to the phenomenon termed "skew".
If the change of the signal OE from the logic state L to the logic state H occurs earlier than the timing of change of the latched signals RBST' and RBSN', a large current tends to flow from the power supply line to the ground line due to the ON-ON state of the p- and n-channel MOSFETs 710 and 711.
On the other hand, if the change of the signal OE from the logic state L to the logic state H occurs later than the timing of change of the latched signals RBST' and RBSN', the output of the output data signal DOUT tends to be delayed.
Thus, it is very difficult to adjust or design the pulse width of the output-enable signal OE so that the ON-ON state of the p- and n-channel MOSFETs 710 and 711 are prevented from occurring.